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| sh graphics/speech processing demonstration system NAV-DS4 application note ade-502-058 rev. 1.0 preliminary 11/25/99 hitachi, ltd.
notice when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. preface this application note covers the hardware and software of the NAV-DS4 navigation sh graphics/speech processing demonstration system developed by hitachi, ltd. it includes a number of practical examples intended for use as reference material when designing a navigation system using an sh3 microcomputer and q2 graphics renderer (however, note that NAV-DS4 does not support gps (global positioning system)). the NAV-DS4 uses a variety of hitachi semiconductor devices, including an sh3 (sh7708) 32- bit risc processor, q2 (hd64411) 2-dimensional (2d) graphics renderer, 16m dram (hm51w18165), and 8m flash memory (hn29wt800). demonstration application software provided with the NAV-DS4 comprises map drawing and display, yuv natural image display, adpcm speech output. all of this software runs on an hi- sh77 real-time operating system conforming to the ?tron standard. operation, performance, and standards as a product are not guaranteed for the NAV-DS4. the operation of the electronic circuits and software included in this application note must be evaluated and confirmed by the user before use in an actual application system. i contents section 1 overview ........................................................................................................... 1 1.1 system specifications...................................................................................................... .. 1 1.2 system configuration....................................................................................................... .3 1.3 drawing and display processing procedure...................................................................... 4 1.4 external appearance of NAV-DS4 ................................................................................... 6 1.5 operating procedures ....................................................................................................... .7 1.6 usage notes ................................................................................................................ ....... 13 section 2 NAV-DS4 software ....................................................................................... 15 2.1 overview of demonstration system.................................................................................. 15 2.2 overall software configuration ........................................................................................ 18 2.3 task configuration......................................................................................................... ... 19 2.4 task functions............................................................................................................. ...... 20 section 3 NAV-DS4 hardware ..................................................................................... 21 3.1 hardware configuration.................................................................................................... 2 1 3.2 operation of mother board and daughter board.............................................................. 23 3.3 sh7708 operating conditions .......................................................................................... 23 3.4 q2 operating conditions................................................................................................... 3 5 3.5 interfaces between sh7708 and peripherals ..................................................................... 48 3.6 sh7708 and peripheral timing charts.............................................................................. 63 1 section 1 overview 1.1 system specifications table 1.1 summarizes the specifications of the navigation graphics demonstration system covered in this application note. table 1.1 navigation graphics demonstration system specifications item specifications notes product code NAV-DS4 product name navigation graphics demonstration system mother board cpu sh-3 (sh7708) internal operating frequency: 60 mhz ram edo-dram (4 mbyte) * 1 sram (256 kbyte) * 2 rom flash memory (8 mbyte) daughter board graphics renderer q2 * 3 operating frequency: 30 mhz ugm edo-dram (4 mbyte) cd-rom drive max. 10x (scsi) * 4 data transfer speed: 1.5 mbytes/sec embedded os hi-sh77 real-time multitasking os conforming to m itron specifications ver. 2.02 graphics processing map data conforms to navigation system researcher? association unified standard display colors 8 bits/pixel: 256 of 260,000 colors 16 bits/pixel: 60,000 colors display size 320 240 functions 5-level reduction/enlargement 4-directional smooth scrolling dot units (up/down/left/right) 360-degree rotation degree units (left rotation/ right rotation) restoration and playback of d yuv- compressed natural images q2 hardware 2 table 1.1 navigation graphics demonstration system specifications (cont) item specifications notes speech processing functions restoration and playback of adpcm-compressed speech * 6 sh3 software notes: 1. edo: extended data out?ynamic random access memory 2. sram: static random access memory 3. q2: quick 2d graphics renderer 4. scsi: small computer system interface 5. tron: the real time operating system nucleus m itron: micro industrial tron 6. adpcm: adaptive delta pulse code modulation 3 1.2 system configuration figure 1.1 shows the system configuration. cd-rom drive with built-in speaker q2 (hd64411) sh-3 (hd6417708) dac edodram (16 mbit 2) sci i/f pc sci i/f edodram (16 mbit 2) flash (8 mbit 8) dac video output block data bus address bus speech i/f line input display monitor tv screen key input block figure 1.1 system configuration this demonstration system consists of a mother board holding a 32-bit risc processor (sh7708: 60 mhz operation), a daughter board holding a graphics renderer (q2: 30 mhz operation), and a cd-rom drive that reads map data from a cd-rom. in graphics processing, the sh7708 handles geometrical operations while the q2 is responsible for rendering (drawing) operations. this reduces the processing load on the sh processor and improves system bus utilization. in speech processing, real-time regeneration of adpcm speech data is possible by means of high- speed processing using the sh7708, enabling the number of dedicated devices used, and system cost, to be reduced. a real-time multitasking os (operating system) conforming the ?tron specifications is incorporated, enabling both independent and parallel processing, and increasing the real-time capabilities of the system. 4 1.3 drawing and display processing procedure figure 1.2 shows the map drawing flow in the NAV-DS4. the procedure is outlined below. 1. management information, text, and map data are read from cd-rom and stored in dram. 2. the sh7708 performs coordinate conversion on the map data and transfers the converted data to dram. 3. the sh7708 regenerates the display list (list of q2 drawing commands) from the coordinate map data in dram, and transfers this to the q2? ugm. 4. the sh7708 enables drawing execution by the q2. the q2. performs drawing in accordance with the display list. the sh7708 can execute other tasks while the q2 is drawing. 5. the q2 uses a double-buffering system with a drawing plane and a display plane , so that the display plane can be displayed during drawing. display control is performed by the q2 itself, without involving the sh7708. 6. when drawing ends, the drawing plane and display plane are switched. screen switching control by the q2 or the sh7708 can be selected. 7. in 8-bit/pixel mode, dot-unit data is converted to any of 256 colors from among 260,000 colors with the color palette (cplt: colpalet). in 16-bit/pixel mode, 60,000 colors can be displayed. 5 monitor rgb d/a cplt i/f q2 rendering unit display unit display list ugm (dram) dram map data (vector data format) text data manage- ment information cd-rom coordinate- converted map data flash memory os (hi-sh77) application drawing library data bus display frame drawing frame sh microcomputer cache cpu bsc polygon4c line . . . . map data, text, management information data transfer map data, text, management information map data, text, management information cd-rom display 1 map data transfer 2 transfer of data after coordinate conversion 3 transfer of data before drawing 4 display list transfer 5 drawing in ugm 6 rgb signal output 7 dram sh microcomputer coordinate conversion processing coordinate-converted map data before drawing display list regeneration processing drawing processing data after drawing processing display processing dram sh microcomputer q2 ugm (dram) q2 2 4 3 1 5 6 7 display list (example) figure 1.2 drawing and display processing flow 6 1.4 external appearance of NAV-DS4 figure 1.3 shows an external view of the NAV-DS4. the NAV-DS4 consists of a mother board, a daughter board, a cd-rom drive, and a monitor. the system is operated by means of operating key switches on the mother board. the operating keys are shown in figure 1.4. scsi cable daughter board operating key switches mother board monitor sh7708 q2 cd-rom drive with built-in speaker figure 1.3 external view of NAV-DS4 menu sw0 sw1 sw2 sw6 sw3 sw7 sw4 sw5 sw8 sw9 sw10 sw11 enter wide area detail sw12 sw13 sw14 sw15 figure 1.4 NAV-DS4 operating key panel layout 7 1.5 operating procedures NAV-DS4 operating procedures are described here. be sure to read the usage notes in the following section before operating the NAV-DS4. (1) demonstration system setup procedure (see figure 1.5) 1. place the mother board, cd-rom drive, and monitor on a table, desk, or similar flat surface as shown in the figure below. 2. connect the daughter board to the mother board connector as shown in the figure. 3. connect the scsi cable and monitor cable. 4. connect the power cords to the cd-rom drive and monitor, plug them into a 100 vac power outlet, and turn on the power. 5. insert a navigation system research association format cd-rom in the prescribed position in the cd-rom drive, and turn on the cd-rom drive power. 6. check steps 2 to 5 again, then plug the power cord connected to the mother board into a 100 vac power outlet, and turn on the power. scsi cable power cord daughter board reset switch mother board monitor sh7708 q2 cd-rom drive cd-rom power switch monitor cable graphics processing unit power cable figure 1.5 NAV-DS4 setup procedure diagram 8 (2) operations after setup (examples) menu enter superh risc engine initial screen no operation necessary menu enter no operation necessary map screen is displayed menu enter up left down right display screen after the initial screen is displayed, map data is read from the cd-rom, drawing is performed, and the result is displayed on the screen. (automatic) when power is turned on, the initial screen is displayed. (automatic) scrolling (in any of 4 directions) continues while the up, down, left, or right key is pressed on the sw board, and stops when the key is released. sw board operations description initial screen on powering on map screen display map screen scrolling 9 north-up display setting adpcm d yuv menu menu enter display screen the map is rotated (in degree units) about the center of the screen while a rotation key on the sw board is pressed. rotation stops when the key is released. pressing the detail key in the sw board displays a map enlarged by one level; pressing the wide area key displays a map reduced by one level. (5 enlargement/reduction levels available) after a map rotation demonstration, press the menu key on the sw board, select ?orth-up display setting,?and press the enter key. the display will return to its state prior to the rotation. sw board operations description map screen enlargement/reduction map screen rotation setting after rotation wide area detail menu enter wide area detail reduce enlarge left rotation right rotation menu enter wide area detail menu menu screen up enter down 10 (3) yuv demonstration operations display screen the d yuv natural image display demonstration is an automatic demonstra- tion (no key input required). press the menu key to display the menu screen, and move the cursor to d yuv with the up/down keys. the d yuv demonstration is started by pressing the enter key. the automatic demonstration ends after approximately one minute, and the map screen is displayed again. sw board operations description starting d yuv demonstration d yuv demonstration end of d yuv demonstration menu enter wide area detail menu enter wide area detail fixed-north d yuv menu menu enter wide area detail menu up enter down adpcm 11 (4) adpcm demonstration operations display screen pressing a phrase playback key plays the phrase assigned to that key. the phrase playback keys arranged so that a sentence can be constructed from four phrases (including chimes) by selecting a phrase from each row in turn, starting at the top row and moving downward. (the phrase arrangement is shown on the left.) press the menu key to display the menu screen, and move the cursor to ?dpcm?with the up/down keys. the adpcm demonstration is started by pressing the enter key. sw board operations description starting adpcm demonstration phrase playback menu enter wide area detail fixed-north d yuv menu menu enter wide area detail menu up enter down adpcm fixed-north d yuv menu adpcm : phrase playback keys 01 2 3 45 6 7 89 1011 12 13 14 15 2 4 5 6 8 10 12 13 14 pin-pon o-yo-so ko-no-sa-ki ryou-ki-n-jo-no-sa-ki ichi-ki-ro-mei-to-ru-de ni-ki-ro-mei-to-ru-de ji-ta-ku-de-su mo-ku-te-ki-chi-de-su de-gu-chi-de-su chimes approximately ahead beyond the tollbooth 1 km 2 km your home your destination the exit keys and corresponding phrases key no. phrase meaning 12 menu enter display screen pressing the sentence playback key (enter) will play the recorded phrases as a sentence. pressing the record key (detail) will record the phrase played immediately before. the maximum number of recordings is set at 5. pressing the delete key (wide area) will delete the phrase recorded immediately before. this is used to delete a phrase recorded by mistake. pressing the end key (menu) will end the adpcm demonstration and display the map screen again. sw board operations description phrase recording/deletion sentence playback ending adpcm demonstration wide area detail menu enter wide area detail phrase recording menu enter wide area detail end fixed-north adpcm d yuv menu fixed-north adpcm d yuv menu deletion sentence playback 13 1.6 usage notes 1. the power supply must be 100 vac. the NAV-DS4 can be used in both 50 hz and 60 hz regions. 2. always grip the plug when connecting or removing a power cord. 3. system damage, fire, or electric shock may result if a power cord, power cable, or flat cable is stretched, bent, extended, touched with wet hands, or inserted the wrong way round. 3. this system is a navigation demonstration unit, and is not covered by the same after-sales service warranty as other hitachi products. 5. this system has been developed for use under normal environmental conditions (normal temperature and humidity). special consideration has not been given to variations in environmental conditions or secular change. 6. if a demonstration does not operate normally (fails to work when power is turned on) or halts, press the reset button. if this does not restore normal operation, disconnect and the reconnect the mother board power supply. if repeated use of these methods fails to restore normal operation, consult the manufacturer. 7. if the cd-rom drive races out of control, turn of the power immediately. 8. remove any dust from cd-rom disks before use, as this may prevent data from being read. 15 section 2 NAV-DS4 software 2.1 overview of demonstration system the NAV-DS4 can execute the following four kinds of demonstration. 1. map drawing and display demonstration (scrolling, zooming, rotation) map data is read from a navigation system researcher? association format cd-rom and drawing and display are performed. the drawn map can be scrolled up, down, left, or right in dot units, enlarged or reduced in 5 stages, and rotated through 360 degrees. 2. natural image ( yuv image) display demonstration natural image data that has undergone yuv compression is read from a navigation system researcher? association format cd-rom, high-speed conversion from yuv data to rgb data is performed using the q2, and the result is displayed. during display, the converted data is enlarged/reduced, transformed, rotated, etc., using the high-speed drawing functions of the q2. 3. adpcm speech playback demonstration speech data that has undergone adpcm compression is read from a navigation system researcher? association format cd-rom, restored using adpcm restoration middleware, and played via the speaker. operations for these demonstrations are carried out by means of the key switches on the board. table 2.1 lists the key functions, and figure 2.1 shows the overall NAV-DS4 demonstration software configuration. 16 table 2.1 key functions key functions function mark assigned no. in map drawing in menu selection in adpcm demonstration scrolling 5 to look above display map screen selects item above reads adpcm speech data d to look below display map screen selects item below reads adpcm speech data 8 to look to left of display map screen reads adpcm speech data a to look to right of display map screen reads adpcm speech data rotation 7 left (anticlockwise) rotation 3 right (clockwise) rotation enlargement/ reduction wide area b reduces display map deletes data recorded immediately before detail f enlarges display map records selected data menu selection enter 9 starts selected application outputs recorded data as sentence menu 1 displays menu screen ends adpcm demonstration other 2 reads adpcm speech data 4 reads adpcm speech data 6 reads adpcm speech data c reads adpcm speech data e reads adpcm speech data 0 ? invalid (pressing this key has no effect). 17 NAV-DS4 demonstration initialization cpu register settings q2 register settings set map display coordinate initial values set mode decision variable to map mode initial screen display read cd-rom disk label drawing parameters unit management information until reset or power-off read cd-rom unit data map drawing and display until menu key input until demonst- ration selection input demonstration selection input key input menu display d yuv automatic demonstration fixed-north display d yuv demonstration adpcm demonstration until key input until menu key input scroll processing scroll keys zoom keys rotate keys enlargement/ reduction processing rotation processing menu display key input phrase output phrase recording recorded phrase deletion continuous playback of recorded phrases start of demonstration end of demonstration figure 2.1 overall NAV-DS4 demonstration software configuration 18 2.2 overall software configuration the NAV-DS4 incorporates an hi-sh77 real-time multitasking operating system conforming to the ?tron standard. application programs are divided into processing units which are recorded in the kernel as ?asks.?a maximum of 1023 tasks can be recorded. the kernel identifies and manages each task by means of a number from 1 to 1023 called the task id. tasks are activated via the kernel by means of asynchronously generated events such as key input operations. interrupt handlers are also created to handle processing by interrupts. when an interrupt occurs, control is passed to an interrupt handler via an exception service routine in the kernel. the nav- ds4 uses a variety of interrupts, including key input, scsi protocol control, and cd-rom drive data reads. having the operating system manage and control program flow in this way enables efficient, real- time demonstration operations to be implemented. the relationship between tasks and the kernel in the NAV-DS4 is illustrated in figure 2.2. for detailed specifications of the hi-sh77 operating system, refer to the hi-sh77 user? manual and construction manual. events kernel system calls task 1 application execution interrupt handler key input scsi control task 2 application execution system calls execution figure 2.2 relationship between tasks and kernel 19 2.3 task configuration figure 2.3 shows the configuration of the tasks and interrupt handlers recorded in the kernel by the NAV-DS4. key input control tasks menu control task activation scroll control task activation rotation control task activation enlargement/ reduction control task activation adpcm control task activation d yuv control block kernel menu control task scroll control task rotation control task enlargement/ reduction control task adpcm control task drawing/ display control block mode control block cd-rom control block drawing/ display control block drawing/ display control block cd-rom control block drawing/ display control block cd-rom control block adpcm control block interrupt handlers scsi control block cd-rom data read activation key input control task speech output control key no. read : indicates that the task is activated by issuance of a processing request (system call) to the kernel. activation figure 2.3 task and interrupt handler configuration 20 2.4 task functions table 2.2 summarizes the functions of the tasks and interrupt handlers recorded in the kernel by the NAV-DS4. table 2.2 summary of functions (1/3) task name function key input control issues a processing request (system call) to the kernel according to the key input, activating a task. the meaning of the keys depends on the key input mode. 1. in map mode (normal mode) performs scroll control task activation by means of the up/down/left/right arrow keys, rotation control task activation by means of the rotate keys, enlargement/reduction control task activation by means of the wide area and detail keys, and menu control task activation by means of the menu key. 2. in menu operation mode selects a menu display item by means of the up/down arrow keys, and activated the task corresponding to the item. 3. in adpcm mode performs activation of adpcm control tasks corresponding to the up/down/left/right arrow keys, rotate keys, wide area and detail keys, and enter and menu keys. menu selection control draws the menu screen, and sets the menu operation mode, adpcm demonstration mode, or speech synthesis demonstration mode from map mode according to the menu display items scroll control reads map data from the cd-rom, creates a display list, and draws a map in the q2? multi-valued source area. in scroll movement processing, drawing is performed while updating coordinate locations from the multi-valued source area to the display area at each q2 vertical sync signal. rotation control performs coordinate conversion of map data by means of affine transformation processing, creates a display list, and draws in the display area with the q2. enlargement/ reduction control reads wide-area or detailed map data from the cd-rom, creates a display list, and draws in the display area with the q2. adpcm control reads adpcm data from the cd-rom, and performs data expansion processing. 21 section 3 NAV-DS4 hardware 3.1 hardware configuration the NAV-DS4 mother board consists of an sh7708 32-bit risc microcomputer, various kinds of memory (an hm51w18165aj-6 2-mbyte dram, hn29wb800t-8 8-mbyte flash memory, and hn67w1664-jp-12 256-kbyte static ram), an hd151015 level shifter, hitachi hd74lvc series cmos logic semiconductor devices, an rs-232c control ic, scsi control ic, d/a converter, and three fpgas (field programmable gate arrays) for key input control, scsi control, and speech control. the daughter board comprises an hd64411f (q2), hm5118165att-7 2-mbyte dram, and hd153510 f50 (dac) hitachi semiconductor devices, and an rgb encoder. tables 3.1 and 3.2 list the functions of the lsis mounted on the NAV-DS4? mother board and daughter board, and figure 3.1 shows the hardware configuration. table 3.1 functions of lsis mounted on mother board mounted lsi device function hd6417708f60a (sh7708) 32-bit risc microcomputer hm51w18165aj-6 16mbit-edo-dram hm67w1664-jp-12 1mbit-sram hn29wb800t-8 8mbit-flash memory hd151015 level shifter hd74lvc244a unidirectional level shifter hd74lvc245a bidirectional level shifter hd74lvc08 and gate hd74lvc00 nand gate hd74lvc32 or gate hd74lvc04 inverter (not) hd74lvc14 schmitt trigger inverter epf8282atc100-3 key input control (fpga) epf8452atc100-3 speech output (fpga) epm7032lc44-6 scsi control (fpga) sym53cf96-2 scsi controller m pd6376gs dac max233acwp rs-232c controller lti086ct-3.3 dd conversion lsi lti086ct-5 dd conversion lsi 22 table 3.2 functions of lsis mounted on daughter board mounted lsi device function hd64411f (q2) quick 2d graphics renderer hm5118165att-7 16mbit-edo-dram hd153510f50 8bit-3chdac hd74ls04fp inverter (not) cxa1645 rgb encoder mother board personal computer cd-rom drive rs-232c interface scsi controller scsi control fpga sci cpu sh7708 daughter board ugm: dram (edo mode) 4 mbytes 16 mbits 16 mbits q2 image output block rgb encoder dac tv monitor rgb monitor expansion unit expansion connector key input fpga 8 mbytes flash memory dram (edo mode) 8 mbits 8 mbits 8 mbits 8 mbits 8 mbits 8 mbits 8 mbits 8 mbits 16 mbits 16 mbits 4 mbytes 1 mbit 256 kbytes sram 1 mbit key input block address bus data bus (32-bit) speech output block speech output fpga dac speaker note: the mother and daughter boards are connected by a board-to-board connector. figure 3.1 hardware configuration 23 3.2 operation of mother board and daughter board mother board operations are as follows: 1. the mother board is controlled by the sh7708. 2. controls the q2 on the daughter board. 3. controls the external cd-rom drive connected via a scsi interface. 4. controls the 16 keys. 5. outputs 16-bit stereo speech data. 6. when a pc is connected to the sci connector, performs serial data communication with the pc. daughter board operations are as follows: 1. controls drawing processing and display processing by the q2. 2. outputs images to the tv monitor and rgb monitor. 3.3 sh7708 operating conditions (1) operating clock: in the NAV-DS4, a 30 mhz crystal oscillator is used for the sh7708? external input clock. the clock operating mode is set to mode 0 by external switching of the mode pins (md0, md1, and md2). the frequency multiplication ratio of the sh7708? on-chip pll circuit is set to 2, and the internal clock and peripheral clock division ratios are set to 1 and 1/2, respectively, in the frequency control register (frqcr), so that the sh7708?s internal clock (i?) is 60 mhz and its peripheral clock (p?) is 30 mhz. the sh7708 clock operating mode pin settings and corresponding operations used in the NAV-DS4 are shown in table 3.3, and the frequency control register (frqcr) settings and corresponding operations in figure 3.2. table 3.3 clock operating mode pin settings and operations pin names clock input/ output clock operating mode md2 md1 md0 supply source/ output pll circuit 1 on/off divider 1 input cki0 frequency internal clock mode 0 0 0 0 extal/ ckio on pll circuit 1 output extal frequency resulting from applying pll circuit 1 frequency multiplication ratio and divider 1 division ratio to cki0 24 initial value bit: 15 ? ckoen = 1 : clock is output from cki0 pin. ? pllen = 0 : pll circuit 1 is not used. (as clock operating mode 0 is used, this bit is invalid.) ? pstby = 0 : pll standby is not performed. (as clock operating mode 0 is used, this bit is invalid.) ? stc1, 0 = 01 : pll circuit 1 frequency multiplication ratio is 2. ifc1, 0 = 00 : internal clock frequency division ratio is 1. pfc1, 0 = 01 : peripheral clock frequency division ratio is 1/2. set value 14131211109876543210 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 cko en pll en p stby stc 1 stc 0 ifc 1 ifc 0 pfc 1 pfc 0 figure 3.2 frequency control register (frqcr) settings and operations (2) pin functions: the sh7708 has a number of multiplex pins. the multiplex pins and pin functions used by the NAV-DS4 are listed in table 3.4. 25 table 3.4 multiplex pins and pin functions 5 8 9 10 11 12 13 14 84 85 86 103 104 108 109 117 118 119 120 123 124 126 129 130 d23 d22 d21 d20 d19 d18 d17 d16 md2 md1 md0 md4 md3 _cs6 _cs5 _we3 _we2 _cashh _cashl _we1 _we0 _casll _ras md5 pin no. port7 port6 port5 port4 port3 port2 port1 port0 rxd txd sck _ce2b _ce2a _ce1b _ce1a dqmuu dqmul _cas2h _cas2l dqmlu dqmll _cas _ce _ras2 _iciowr _iciord _oe data bus data bus data bus data bus data bus data bus data bus data bus operating mode (clock operating mode setting) operating mode (clock operating mode setting) operating mode (clock operating mode setting) operating mode (area 0 bus width setting) operating mode (area 0 bus width setting) chip select 6 chip select 5 write strobe signal for d31?24 write strobe signal for d23?16 cas signal for d31?24 cas signal for d23?16 write strobe signal for d15?8 write strobe signal for d7?0 cas signal for d7?0 ras signal operating mode (entire-space endian setting) pin name on recovery after reset (in ) (after elapse of 50 [ns]) data bus data bus data bus data bus data bus data bus data bus data bus serial data reception and break state detection serial data transmission and break state sending serial clock input/output and i/o port operating mode (area 0 bus width setting) operating mode (area 0 bus width setting) chip select 6 chip select 5 write strobe signal for d31?24 write strobe signal for d23?16 cas signal for d31?24 cas signal for d23?16 write strobe signal for d15?8 write strobe signal for d7?0 cas signal for d7?0 ras signal operating mode (entire-space endian setting) function on reset (in ) 26 (3) interrupt handling: the NAV-DS4 uses irl interrupts. the key input fpga has an interrupt priority encoder function, and inputs levels to pins _irl3?irl0 according to the _inrq15?inrq0 pin priority levels shown in table 3.5. figure 3.3 shows the interrupt priority encoder peripheral block diagram. table 3.5 _inrq15?inrq0 pins and interrupt priority order pin interrupt priority level _irl3 _irl2 _irl1 _irl0 interrupt priority order _inrq15 15 0000 high _inrq14 14 0001 _inrq13 13 0010 _inrq12 12 0011 _inrq11 11 0100 _inrq10 10 0101 _inrq9 9 0110 _inrq8 8 0111 _inrq7 7 1000 _inrq6 6 1001 _inrq5 5 1010 _inrq4 4 1011 _inrq3 3 1100 _inrq2 2 1101 _inrq1 1 1110low 27 _inrq15 _inrq14 _inrq13 _inrq12 _inrq11 _inrq10 _inrq9 _inrq8 _inrq7 _inrq6 _inrq5 _inrq4 _inrq3 _inrq2 _inrq1 _irl3 _irl2 _irl1 _irl0 interrupt requests expansion connector q2 (daughter board) speech output fpga scsi key input fpga scsi control fpga interrupt priority encoder cpu: sh7708 figure 3.3 interrupt priority encoder peripheral block diagram 28 (4) address map: in the sh7708, the physical address space can be managed as seven separate areas, numbered 0 to 6, each of up to 64 mbytes in size. the address map of the NAV-DS4 is shown in figure 3.4. the function and bus cycle state of each area are set with the bus control register (bcr1). bus control register (bcr1) settings and corresponding operations are shown in figure 3.5. 32 16 32 32 16 32 32 h'00000000 h'007fffff h'03ffffff h'04000000 h'04000041 h'07ffffff h'08000000 h'0803ffff h'0bffffff h'0c000000 h'0c3fffff h'0fffffff h'10000000 h'103fffff h'11000000 h'110005ff h'13ffffff h'14000000 h'14000007 h'14000013 h'14000023 h'17ffffff h'18000000 h'1bffffff area 0 area 1 area 2 area 3 area 4 area 5 area 6 speech output fpga key input fpga expansion connector q2 1536 bytes ugm (dram) 4 mbytes dram 4 mbytes sram 256 kbytes scsi flash memory 8 mbytes terminal address depends on what is connected. data bus width set value [bits] use ? programs ? character fonts ? monitor program ? cd-rom data reading ? monitor program work area ? program work area ? map data ? display list ? source/work area ? frame buffers ? q2 on-chip registers ? speech data output ? key input control ? interrupt priority encoder ? expansion rom connection ? speech recognition unit connection figure 3.4 NAV-DS4 address map 29 initial value bit: 15 ? hizcnt = 0 : _ras and _cas signals become high-impedance in standby mode and when bus is released. ? a0bst1, 0 = 00 : area 0 is accessed as ordinary memory. ? a5bst1, 0 = 00 : area 5 is accessed as ordinary memory. ? a6bst1, 0 = 00 : area 6 is accessed as ordinary memory. ? dramtp2, 1, 0 = 100 : area 2 is accessed as ordinary memory, and area 3 as dram. ? a5pcm = 0 : area 5 is accessed as ordinary memory. ? a6pcm = 0 : area 6 is accessed as ordinary memory. set value 14131211109876543210 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 hiz cnt endi an a0 bst1 a0 bst0 a5 bst1 a5 bst0 a6 bst1 a6 bst0 dram tp2 dram tp1 dram tp0 a5 pcm a6 pcm figure 3.5 bus control register (bcr1) settings and operations (5) memory bus width and data format: the sh7708? memory bus width is set for each space. flash memory is connected to area 0, and mode pins md3 and md4 are set by an external switch to give a 32-bit bus width. the md5 mode pin is set by an external switch to designate a big-endian data format. mode pin settings and the corresponding operations are shown in table 3.6. the bus width of areas 1 to 6 is set in bus control register 2 (bcr2). bus control register 2 (bcr2) settings and the corresponding operations are shown in table 3.6. however, the dram interface bus width is set in the individual memory control register (mcr). see (7) below for details of this register. table 3.6 mode pin settings and states pin name description md5 md4 md3 endian area 0 bus width 0 1 1 big 32 bits 30 initial value bit: 15 ? a6sz1, 0 = 11 : area 6 bus width is set to 32 bits. ? a5sz1, 0 = 11 : area 5 bus width is set to 32 bits. ? a4sz1, 0 = 10 : area 4 bus width is set to 16 bits. ? a3sz1, 0 = 11 : area 3 bus width is set to 32 bits. ? a2sz1, 0 = 11 : area 2 bus width is set to 32 bits. ? a1sz1, 0 = 10 : area 1 bus width is set to 16 bits. ? porten = 0 : d23?16 are not used as port pins. set value 14131211109876543210 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 a6 sz1 a6 sz0 a5 sz1 a5 sz0 a4 sz1 a4 sz0 a3 sz1 a3 sz0 a2 sz1 a2 sz0 a1 sz1 a1 sz0 port en figure 3.6 bus control register 2 (bcr2) settings and operations (6) wait control: with some peripheral devices, data bus drive is not immediately switched off when the read signal from the sh7708 is switched off. therefore, when consecutive accesses that span a number of areas are performed, or when a switch is made to write access immediately after read access, for example, there is a possibility of a data collision on the data bus. for this reason, wait control register 1 (wcr1) is set to provide automatic idle cycle insertion. wait control register 1 (wcr1) settings and the corresponding operations are shown in figure 3.7. wait state insertion cycle specifications for each area are made in wait control register 2 (wcr2). the data access pitch specification for burst access is also made in this register. the flash memory (hn29wb800t-8) connected to area 0, can be accessed in four cycles with two wait states inserted. wait control register 2 (wcr2) settings and the corresponding operations are shown in figure 3.8. 31 initial value bit: 15 when switching from one area to another, or when switching from read access to write access in the same area ? a6iw1, 0 = 01 : for area 6, one idle cycle is inserted. ? a5iw1, 0 = 01 : for area 5, one idle cycle is inserted. ? a4iw1, 0 = 01 : for area 4, one idle cycle is inserted. ? a3iw1, 0 = 01 : for area 3, one idle cycle is inserted. ? a2iw1, 0 = 01 : for area 2, one idle cycle is inserted. ? a1iw1, 0 = 01 : for area 1, one idle cycle is inserted. ? a0iw1, 0 = 01 : for area 0, one idle cycle is inserted. set value 14131211109876543210 0 0 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 a6 iw1 a6 iw0 a5 iw1 a5 iw0 a4 iw1 a4 iw0 a3 iw1 a3 iw0 a2 iw1 a2 iw0 a1 iw1 a1 iw0 a0 iw1 a0 iw0 figure 3.7 wait control register 1 (wcr1) settings and operations initial value bit: 15 ? a6w2, 1, 0 = 111 : number of wait states inserted for area 6 = 10 ? a5w2, 1, 0 = 001 : number of wait states inserted for area 5 = 1 ? a4w2, 1, 0 = 100 : number of wait states inserted for area 4 = 4 ? a3w1, 0 = 00 : dram _cas assertion width = 1 state ? a1?w1, 0 = 01 : number of wait states inserted for areas 1 and 2 = 1 ? a0w2, 1, 0 = 010 : number of wait states inserted for area 0 = 2 set value 14131211109876543210 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 a6 w2 a6 w1 a6 w0 a5 w2 a5 w1 a5 w0 a4 w2 a4 w1 a4 w0 a3 w1 a3 w0 a1? w1 a1? w0 a0 w2 a0 w1 a0 w0 figure 3.8 wait control register 2 (wcr2) settings and operations 32 (7) memory control: in the NAV-DS4, edo mode 16-mbit dram (hm51w18165aj-6) is connected to area 3. dram access in edo mode requires a maximum of six cycles, with tr and trw cycles inserted, and a minimum of two cycles when consecutive addresses are accessed (using burst access). cas-before-ras refreshing is used. the _ras and _cas timing, burst control, address multiplex specifications, and refresh control specifications are made in the individual memory control register (mcr). individual memory control register (mcr) settings and the corresponding operations are shown in table 3.9. the refresh period, presence or absence of interrupt generation, and the interrupt generation period, are specified in the refresh timer control/status register (rtcsr). the upper limit of the refresh timer counter (rtcnt) is set in the refresh timer constant register (rctor). refresh timer control/status register (rtcsr) settings and the corresponding operations are shown in figure 3.10, and refresh timer constant register (rctor) settings and operations in figure 3.11. initial value bit: 15 settings when dram is connected to area 3 ? tpc1, 0 = 01 : minimum number of cycles until _ras is next asserted after being negated = 2 ? rcd1, 0 = 01 : _ras?cas assertion delay time = 2 cycles ? trwl1, 0 = 00 : not set ? tras1, 0 = 01 : _ras assertion period in _cas-before-_ras refreshing = 3 cycles ? be =1 : burst access is performed ? sz = 1 : bus size is 32 bits. ? amx1, 0 = 10 : address multiplex setting = 10-bit column address product used ? rfsh = 1 : refresh control specification = refresh performed ? rmode = 0 : _cas-before-_ras refreshing is performed. ? edomode = 1 : set to edo mode. (data sampling timing for read cycle is cki0 rise. _ras signal negation timing is 1/2 machine cycle after cki0.) set value 14131211109876543210 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 tcp1 tcp0 rcd1 rcd0 trwl 1 trwl 0 tras 1 tras 0 sz be amx1 amx0 rfsh rmo de edo mode figure 3.9 individual memory control register (mcr) settings and operations 33 initial value bit: 15 ? cmf = 0 : status flag indicating that the refresh timer counter (rtcnt) and refresh time constant register (rtcor) values match. ? cmie = 0 : interrupt requests by cmf are disabled. ? cks2, 1, 0 = 001 : selects refresh timer counter (rtcnt) input clock. (cki0/4) ? ovf = 0 : status flag indicating that the number of refresh requests indicated in the refresh count register (rfcr) has exceeded the number indicated by lmts. ? ovie = 0 : interrupt requests by ovf are disabled. ? lmts = 0 : count limit value compared with the number of refresh requests indicated in the refresh count register (rfcr) (the count limit value is set to 1024). set value 14131211109876543210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 cmf cmie cks2 cks1 cks0 ovf ovie lmts figure 3.10 refresh timer control/status register (rtcsr) settings and operations initial value bit: 15 ? sets the upper limit of the rtcnt counter. (lower 8 bits) ? calculation formula: set value 14131211109876543210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 rtcnt value = = = = 117.1875 ? h'75 dram refresh period [s] refresh timer counter (rtcnt) period [s] 16 10 e3 [s] 1024 [cycles] 16 10 e3 1024 30 10 6 4 1 ( cki0/4 ) [ c y cles ] figure 3.11 refresh time constant register (rtcor) setting and calculation formula 34 (8) cache memory: the sh7708 has on-chip cache memory. use of 8-kbyte cache (normal mode) or 4-kbyte cache and 4-kbyte ram (ram mode) can be selected. a mixed instructions/data type 4-way set-associative configuration (normal mode) or 2-way set-associative configuration (ram mode) can be selected. with the NAV-DS4, normal mode, using 8-kbyte cache memory, is set. the operating mode is set in the cache control register (ccr). cache control register (ccr) settings and the corresponding operations are shown in table 3.12. initial value bit: 31 ? ra = 0 : normal mode (8-kbyte cache) ? cf = 1 : v, u, and lru bits of all cache entries are cleared to 0. ? wt = 0 : write-back mode ? ce = 1 : cache is used. set value 543210 0 0 0 0 ra 0 0 0 0 0 cf 0 1 0 0 wt 0 0 ce 0 1 figure 3.12 cache control register (ccr) settings and operations 35 3.4 q2 operating conditions (1) operating clocks: there are two q2 clocks, the drawing clock (clk0) and the display clock (clk1). the sh7708? cki0 (30 mhz) output is input via a level shifter as the drawing clock (clk0). for the clock operating mode, the mode pins (mode0, mode1, are mode2) are set to mode 3 by means of an external switch. the q2 clock operating mode pin settings used by the NAV-DS4, and the corresponding operations, are shown in table 3.3. the q2 display clock (clk1) is provided by a 14.318 mhz crystal oscillator. a display dot clock of 7.15 mhz (1/2 the clk1 clock frequency) provided by the q2? on-chip frequency divider is set by means of the q2? display mode register (dsmr). see (2) below for details of this register. table 3.3 clock operating mode pin settings and states clock operating pin names multiplication mode md2 md1 md0 operation on/off internal clock mode 3 0 1 1 normal operating state off same as external input clock (2) interface control: overall q2 control is performed by settings in a group of registers called the interface control registers (frqcr). these registers are as follows: system control register (sysr): sets q2 system operation. status register (sr): reads the q2?s internal status externally (read-only). status register clear register (srcr): clears the corresponding status register contents. interrupt enable register (ier): sets the conditions for interrupt generation from the q2 to the cpu. memory mode register (memr): sets the size and number of ugm memories. display mode register (dsmr): settings related to q2 display operations. rendering mode register (remr): settings related to q2 drawing operations. input data conversion mode register (iemr): settings related to format conversion of input data from the cpu. interface control register (frqcr) settings used by the NAV-DS4, and the corresponding operations, are shown in figures 3.13 to 3.18. 36 bit: 15 sres = 0 : command execution is enabled. dres = 0 : display synchronization operation is started. the values stored in the ugm are den = 1 output from the dd pin as display data. dc = 0 : display frame buffer switching is not performed in manual display change mode. = 1 : display frame buffer switching is performed in manual display change mode. ? rs = 0 : rendering is not started. = 1 : rendering is started. ? dbm = 01 : auto rendering mode is set. = 10 : manual display change mode is set. ? dma = 00 : normal mode is set. ? ccm = 0000 : normal mode is set. note: the values of dc, rs, and dbm are chan g ed accordin g to the processin g executed. set value 14131211109876543210 sres 0 dres 0 den 1 0 0 0 dc 0 or 1 rs 0 or 10 or 11 or 0000000 dbm dma ccm figure 3.13 system control register (sysr) settings and operations bit: 15 ? tve = 0 : tv synchronization error flag interrupt is not enabled. ? fre = 0 : frame flag interrupt is not enabled. ? dme = 0 : dma flag interrupt is not enabled. ? cee = 0 : command error flag interrupt is not enabled. ? vbe = 0 : vertical blanking flag interrupt is not enabled. = 1 : vertical blanking flag interrupt is enabled. ? tre = 0 : trap flag interrupt is not enabled. ? cse = 0 : command suspend flag interrupt is not enabled. note: the value of vbe is chan g ed accordin g to the processin g executed. set value 14131211109876543210 tve 0 fre 0 dme 0 cee 0 vbe 0 or 1 tre 0 cse 0 0 0 0 0 0 0 0 0 0 figure 3.14 interrupt enable register (ier) settings and operations 37 bit: 15 ? mes = 010 : two 16-mbit drams are used for the ugm. ? mea = 01 : number of row address bits = 10 set value 14131211109876543210 0 0 0 0 0 0 0 0 00 mes 1101 0 0 mea figure 3.15 memory mode register (memr) settings and operations bit: 15 ? ycm = 0 : rgb/ycrcb conversion is not performed. ? dot = 1 : 1/2 the frequency of the clock input from the clk1 pin is used as the display dot clock. ? tvm = 0 : sets master mode in which hsync, vsync, and oddf are output. ? scm = 00 : display output is set to non-interlace. = 10 : interlace sync set for video monitor output. ? ref = 0101 : refresh timing set to 5 cycles. note: the value of scm is changed according to the processing executed. set value 14131211109876543210 0 0 0 0 0 0 ycm 0 dot 1000 or 100101 tvm scm ref figure 3.16 display mode register (dsmr) settings and operations bit: 15 ? mwx = 1 : the ugm x-direction logical coordinate space is set to 1024 pixels. ? gbm = 0 : rendering data bit configuration is set to 8 bits/pixel (in map data processing). = 1 : rendering data bit configuration is set to 16 bits/pixel (in natural image data processing). note: the value of gbm is changed according to the processing executed. set value 14131211109876543210 0 0 0 0 0 0 0 0 0 mwx 1 0 0 0 0 0 gbm 0 or 1 figure 3.17 rendering mode register (remr) settings and operations 38 bit: 15 ? yuv = 00 : sets normal mode in which data conversion is not performed. = 10 : sets mode in which d yuvergb data conversion is performed. (in d yuv data processing) note: the value of yuv is changed according to the processing executed. set value 14131211109876543210 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 0 or 1 0 yuv figure 3.18 input data conversion mode register (iemr) settings and operations (3) memory control: the q2 uses a ugm (unified graphics memory) architecture, in which data of different formats (such as frame buffer area data and font pattern area data) is stored and managed in the same memory. the configuration of the ugm connected to the q2 is determined by settings in a group of registers called the memory control registers (mecr). these registers are as follows: display size register (dsr): sets the display screen size. display start address register (dsar): sets the frame buffer area. display list start address register (dlsar): sets the display list area. multi-valued source area start address register (ssar): sets the multi-valued source area. work area start address register (wsar): sets the work area. dma transfer start address register (dmasr): sets the transfer destination ugm address in dma transfer. dma transfer word count register (dmawr): sets the number of words to be transferred in dma transfer. since dma transfer is not used by the NAV-DS4, no dma transfer start address register (dmasr) or dma transfer word count register (dmawr) settings are made. memory control register (mecr) settings, and the corresponding operations, are shown in figures 3.19 to 3.23. ugm memory maps are shown in figure 3.24, and 3.25. 39 bit: 15 ? dsx = 0100 111111 : the number of display screen dots in the horizontal direction (x direction) is set to 320. dsy = 011101111 : the number of display screen dots in the vertical direction (y direction) is set to 240. set value 14131211109876543210 0 0 0 0 0 0 0011101111 dsy bit: 15 set value 14131211109876543210 0 0 0 0 0 00100111111 dsx figure 3.19 display size register (dsr) settings and operations bit: 15 ? dsa0 = 0000000 : the frame buffer 0 start address is set to ugm address 0h. ? dsa1 = 0000100 : the frame buffer 1 start address is set to ugm address 40000h (in 8-bit/pixel mode). note: the values of the frame buffer 0 and 1 start addresses are changed according to the processing executed. set value 14131211109876543210 0 0 0 0 0 0 0 0 0000 dsa1 0100 bit: 15 set value 14131211109876543210 0 0 0 0 0 0 0 0 0000 dsa0 0000 figure 3.20 display start address register (dsar) settings and operations 40 bit: 15 ? dlsah = 0001001 : bits a22 to a16 of the display list start address. ? dlsal = 00000000000 : bits a15 to a5 of the display list start address. the display list start address is set to ugm address 90000h (in initialization). note: the value of the displa y list start address is chan g ed accordin g to the processin g executed. set value 14131211109876543210 00000 dlsal 000000 0 0 0 0 0 bit: 15 set value 14131211109876543210 0 0 0 0 0 0 0 0 0000 dlsah 1001 figure 3.21 display list start address register (dlsar) settings and operations bit: 15 ? ssah = 001000 : the multi-valued source area start address is set to ugm address 100000h (in 8-bit/pixel data processing). = 000000 : the multi-valued source area start address is set to ugm address 0h (in natural image data processing). note: the value of ssah is chan g ed accordin g to the processin g executed. set value 14131211109876543210 0 0 0 0 0 0 0 0 0001000 0 ssah figure 3.22 multi-valued source area start address register (ssar) settings and operations bit: 15 ? wsah = 0001000 : the work area start address is set to ugm address 80000h (in 8-bit/pixel data processing). = 0011000 : the work area start address is set to ugm address 180000h (in natural image data processing). note: the value of wsah is chan g ed accordin g to the processin g executed. set value 14131211109876543210 0 0 0 0 0 0 0 0 0000 wsah 1000 figure 3.23 work area start address register (wsar) settings and operations 41 123 45 6 789 8 bits/pixel, screen size = 320 240, 16-mbit memory 1 1023 319 f0 f1 0 239 319 639 959 479 719 240 256 496 512 576 1024 h'00000 h'40000 h'80000 h'90000 h'100000 binary source work display list buffer area multi-valued source 1264 1504 1744 2047 figure 3.24 ugm memory map (8-bit/pixel mode) 42 319 679 1023 f0 f1 h'00000 h'80000 h'180000 h'188000 h'1ffffe 240 256 496 512 752 768 784 1023 16 bits/pixel, screen size = 320 240, 16-mbit memory 1 d yuv data expansion area 1 d yuv data expansion area 2 multi-valued source work display list binary source figure 3.25 ugm memory map (16-bit/pixel mode) (4) display control: the q2 performs double-buffering control that switches alternately between the display area and drawing area located in the ugm, making it possible to alternate between high-speed drawing processing and display processing. q2-controlled display timing settings are made in a group of registers called the display control registers (dscr). these registers are as follows: display window register (dswr): sets display screen horizontal and vertical output timing. horizontal synchronization pulse width register (hswr): sets the low-level pulse width of the horizontal sync signal. horizontal scan cycle register (hcr): sets the horizontal scan cycle. vertical synchronization position register (vspr): sets the start position of the vertical sync signal. vertical scan cycle register (vcr): sets the vertical scan cycle. display off output register (door): sets the display data to be output when the display is off. color detection register (cder): detects display color data. display control register (dscr) settings used by the NAV-DS4, and the corresponding operations, are shown in figures 3.26 to 3.31. 43 bit: 15 ? hds = 00010 11110 : the horizontal display start position is set to 5eh. ? hde = 01100 11110 : the horizontal display end position is set to 19eh. ? vds = 0000010000 : the vertical display start position is set to 10h. ? vde = 0100000000 : the vertical display end position is set to 100h. note: hds and hde are set in dot clock units, and vds and vde in raster line units. set value 14131211109876543210 0 0 0 0 0 00100 vde 000000 bit: 15 set value 14131211109876543210 0 0 0 0 0 00000 vds 010000 bit: 15 set value 14131211109876543210 0 0 0 0 0 00110 hde 011110 bit: 15 set value 14131211109876543210 0 0 0 0 0 00001 hds 011110 figure 3.26 display window register (dswr) settings and operations bit: 15 ? hsw = 00 11111 : the low-level pulse width of the horizontal sync signal is set to 1fh. note: hsw is set in dot clock units. set value 14131211109876543210 0 0 0 0 0 0 0 0 0001 hsw 1111 figure 3.27 horizontal synchronization pulse width register (hswr) settings and operations 44 bit: 15 ? hc = 111000110 : one horizontal scan cycle, including the horizontal retrace line interval, is set to 1c6h. note: hc is set in dot clock units. set value 14131211109876543210 0 0 0 0 000111 hc 000110 figure 3.28 horizontal scan cycle register (hcr) settings and operations bit: 15 ? vsp = 0100000011: the start position of the vertical sync signal is set to 103h. note: vsp is set in dot clock units. set value 14131211109876543210 0 0 0 0 0 00100000011 vsp figure 3.29 vertical synchronization position register (vspr) settings and operations bit: 15 ? vc = 100000110 : one vertical scan cycle, including the vertical retrace line interval, is set to 106h. note: vc is set in raster line units. set value 14131211109876543210 0 0 0 0 0 00100000110 vc figure 3.30 vertical scan cycle register (vcr) settings and operations 45 bit: 15 ? dor = 000000 : the r component of the data output in the display-off state is set to 0h. ? dog = 000000 : the g component of the data output in the display-off state is set to 0h. ? dob = 0 11111 : the b component of the data output in the displa y -off state is set to 1fh. set value 14131211109876543210 000000 0 0011 dob 111 0 0 bit: 15 set value 14131211109876543210 0 0 0 0 0 0 0 0000000 0 0 dog dor figure 3.31 display off output register (door) settings and operations (5) input data control: the NAV-DS4 uses the yuv?gb data conversion function of the q2 to implement high-speed natural image drawing. to control yuv data conversion by the q2, settings are made in a group of registers called the input data control registers (idcr). these registers are as follows: image data transfer start address register (isar): sets the transfer destination address for image data transfer. image data size register (idsr): sets the image data size. image data entry register (hcr): used to input the image data to be converted, input data control register (idcr) settings used by the NAV-DS4, and the corresponding operations, are shown in figures 3.32 to 3.34. 46 bit: 15 ? isah = 0000000 : image data transfer destination physical address bits a22 to a16 are set to 0h. ? isal = 001010000000000 : image data transfer destination physical address bits a15 to a0 are set to 2800h. note: the values of isah and isal are chan g ed accordin g to the processin g executed. set value 14131211109876543210 0010100 isal 00000000 0 bit: 15 set value 14131211109876543210 0 0 0 0 0 0 0 0 0000 isah 0000 figure 3.32 image data transfer start address register (isar) settings and operations bit: 15 ? idsx = 00101101000 : the image data x-direction size is set to 360 dots. ? idsy = 1001000000 : the image data y-direction size is set to 240 dots. note: idsx and idsy are set in pixel units. set value 14131211109876543210 0 0 0 0 0 01001 idsy 000000 bit: 15 set value 14131211109876543210 0 0 0 0 000101101000 idsx figure 3.33 image data size register (idsr) settings and operations bit: 15 ? ide : used to input ima g e data. set value 14131211109876543210 ide figure 3.34 image data entry register (ider) setting and operation 47 (6) color palette: the NAV-DS4 uses the q2? on-chip color palette for map drawing in 8- bit/pixel mode, enabling simultaneous display of 256 colors out of a total of 260,000. color palette settings are made using a group of 256 registers called color palette registers (cp000?p255). colors are set using 6 bits for each of r, g, and b. color palette register values are cleared when drawing is performed after changing from 8-bit/pixel mode to 16-bit/pixel mode, so the settings must be made again when returning to 8-bit/pixel mode. color palette register (cp000?p255) settings used by the NAV-DS4 are shown in figure 3.35. bit: 15 note: due to space limitations, it is not possible to show all the color palette set values. set value 14131211109876543210 000000 0 0000000 0 0 bit: 15 set value 14131211109876543210 bit: 15 14 13 12 11 10 9876543210 0 0 0 0 0 0 0 0000000 0 0 b255 g255 r255 bit: 15 set value 14131211109876543210 000000 0 0000000 0 0 set value 0 0 0 0 0 0 0 0000000 0 0 b000 g000 r000 figure 3.35 color palette register (cp000?p255) settings 48 3.5 interfaces between sh7708 and peripherals (1) interface to 5 v operation units: the NAV-DS4 includes both 5 v and 3.3 v operation units. as the sh7708 operates at 3.3 v, it is connected directly to the 3.3 v operation units, but is connected to the 5 v operation units via a level shifter. a decoder using tll circuitry is provided to prevent signal contact between the 3.3 v and 5 v operation units (bidirectional bus only). figure 3.36 shows a block diagram of the interface between the sh7708 and the 5 v operation units. 3.3 v vcca dir a0 vccb _g b0 level shifter: hd151015 5 v a y _1g _2g y a vcc b t/_r _oe a vcc 3.3 v 3.3 v unidirectional level shifter: hd74lvc244a bidirectional level shifter: hd74lvc245a 5 v units decoder _1g and _2g are fixed at gnd so that the 5 v units can be accessed at all times (access is always enabled). output bus ckio input bus bidirectional bus rd/_wr _cs6 _cs5 _cs1 cpu: sh7708 figure 3.36 block diagram of interface to 5 v operation units 49 (2) flash memory interface: the NAV-DS4 is equipped with 8 mbytes of flash memory (hn29wb800t-8), used in byte mode, to hold programs and character fonts. figure 3.37 shows a block diagram of the interface between the sh7708 and the flash memory. a ttl decoder is provided to allow separate access to the upper 4 mbytes and lower 4 mbytes of the 8-mbyte memory. figure 3.38 shows a logic diagram of the flash memory decoder, and table 3.8 gives the corresponding truth table. a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (d24:31) (hh-1) a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (d16:23) (hl-1) a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (d8:15) (lh-1) a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (d0:7) (ll-1) a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (hh-0) a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (hl-0) a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (lh-0) a-1:18 _ce _oe i/o 0:7 flash memory: hn29wb800t-8 (ll-0) (a2:21) (a2:21) (a2:21) (a2:21) (d0:7) (d8:15) (d16:23) (d24:31) (a2:21) (a2:21) (a2:21) (a2:21) data bus d0:31 address bus a2:21 address bus a22, a23 _rd c so _flaoe0 _flaoe1 decoder cpu: sh7708 figure 3.37 block diagram of flash memory interface 50 flash memory: hn29wb800t-8 _flaoe0 flash memory: hn29wb800t-8 _flaoe0 flash memory: hn29wb800t-8 _flaoe0 flash memory: hn29wb800t-8 _flaoe0 flash memory: hn29wb800t-8 _flaoe1 flash memory: hn29wb800t-8 _flaoe1 flash memory: hn29wb800t-8 _flaoe1 flash memory: hn29wb800t-8 _flaoe1 addresses h'00000000 to h'003fffff addresses h'00400000 to h'007fffff cpu: sh7708 _rd a23 a22 decoder figure 3.38 flash memory decoder logic diagram table 3.8 flash memory decoder truth table input output _rd a23 a22 _flaoe0 _floe1 llllh ? address h'00000000?'003fffff selection llhh l ? address h'00400000?'007fffff selection lhl h h lhhh h hl l h h hl h h h hhl h h hhh h h 51 (3) dram interface: the NAV-DS4 is equipped with two edo mode 16-mbit drams (hm51w18165aj-6), giving a total of 4 mbytes, for use as working memory, used with a 32-bit bus width. cas-before-ras mode is used for refreshing. figure 3.39 shows a block diagram of the interface between the sh7708 and the drams. dram: hm51w18165aj-6 a0:9 _ras _we _ucas _lcas _oe i/o 0:15 (a2:11) (d16: 31) dram: hm51w18165aj-6 a0:9 _ras _we _ucas _lcas _oe i/o 0:15 (a2:11) (d16: 15) _ras rd/_wr _cashh _cashl _caslh _casll cpu: sh7708 data bus d0:31 address bus a2:11 figure 3.39 block diagram of edo-dram interface 52 (4) sram interface: the NAV-DS4 is equipped with two 1-mbit srams (hm67w1664jp-12), giving a total of 256 kbytes, for use as working memory, used with a 32-bit bus width. figure 3.40 shows a block diagram of the interface between the sh7708 and the srams. a0:15 _cs _oe _we _ub _lb sram: hm67w1664jp-12 i/o 9:16 i/o 1:8 (d24:31) (d16:23) (a2:17) data bus d0:31 address bus a2:17 _cs2 _rd rd/_wr _we3 _we2 _we0 _we1 cpu: sh7708 a0:15 _cs _oe _we _ub _lb sram: hm67w1664jp-12 i/o 9:16 i/o 1:8 (d8:15) (d0:7) (a2:17) note: the area inside the dotted line is ttl circuitry. figure 3.40 block diagram of sram interface 53 (5) q2-ugm interface: the NAV-DS4 has a q2 (hd64411f) and two edo mode 16-mbit drams (hm5118165att-7) (4 mbytes), used as the ugm, mounted on its daughter board. a 30 mhz clock is supplied from the sh7708 on the mother board as the drawing clock (clk0). accesses from the sh7708 to the q2 are of two kinds: ugm accesses and accesses to the q2? on-chip registers. the decoder for access selection consists of ttl circuitry. figure 3.41 shows a logic diagram of the ugm/q2 on-chip register selection decoder, and table 3.9 gives the corresponding truth table. as ugm access is performed by cpu transfer, and does not use the dma controller, the q2? _dack pin is fixed high and the _dreq pin is left open. figure 3.42 shows a block diagram of the q2 peripheral interface. decoder _cs0 _cs1 q2: hd64411f cpu: sh7708 _cs4 a24 figure 3.41 ugm/q2 on-chip register selection decoder logic diagram table 3.9 ugm/q2 on-chip register selection decoder truth table input output _cs4 a24 _cs0 _cs1 lllh ? ugm selection lhh l ? q2 on-chip register selection hl h h hh h h 54 a1:22 d0:15 _cs0 _cs1 _rd _we0 _we1 _dack _dreq _wait mode0 mode1 mode2 test clk0 clk1 cap0 _irl _reset cpuvcc vcc pllvcc cpugnd gnd pllgnd disp cde oddf _hsync/_exhsync _vsync/_exvsync _csync dd0:17 fclk dclk md0:15 ma0:11 _mwe _mucas _mlcas _moe _mras0 _mras1 q2: hd64411f a1:22 d0:15 _cs4 a24 _rd _we0 _we1 _wait _irl0 _irl1 _irl2 _irl3 _reset ckio reset switch cpu: sh7708 decoder * 1 * 2 open 3.3 v pull-up resistor 10 k w 5 v h h l open level shifter 30 mhz crystal oscillator 14.31818 mhz 470 pf 3.3 v 5 v interrupt priority encoder display unit notes: 1. ugm/q2 on-chip register selection decoder 2. wait signal from expansion connector a0:9, nc6:7 _we _ucas _lcas _oe _ras d0:15 dram: hm5118165att-7 ugm a0:9, nc6:7 _we _ucas _lcas _oe _ras d0:15 dram: hm5118165att-7 figure 3.42 block diagram of q2 peripheral interface 55 (6) q2-display unit interface: an 8-bit 3-channel dac (hd153510f50) and an rgb/video encoder (cxa1645) are mounted on the daughter board, and connected to the q2, as the display unit. the display unit generates analog rgb signals and ntsc video signals from the 18-bit output from q2 pins dd0 to dd17. control of the resolution, the horizontal and vertical sync signals, etc., is performed by the q2. a 14.318 mhz signal is supplied from the crystal oscillator on the daughter board as the display clock (clk1). figure 3.42 shows a block diagram of the display unit. a vcc r_in g_in b_in sync_in sc_in gnd cv_out ytrap c1; 0.1 m f da2:7 db2:7 dc2:7 _blank dotck ioa iob ioc _hsync/_exhsync _vsync/_exvsync _csync fclk dd0:17 disp dclk clk1 r_out g_out b_out rgb encoder: cxa1645m c2; 33 pf tv monitor 8-bit dac: fhd153510f50 q2: hd64411f crystal oscillator 14.31818 mhz rgb output video output connect c1 (0.1 f) and c2 (33 pf) between avcc and gnd and to the ytrap pin. if c1 and c2 are not provided, color drift may occur in ntsc display images. with ntsc video output, set bit 5 = 1 and bit 4 = 0 (interlace sync mode) as the scan mode (scm) setting in the q2 display mode register (dsmr). figure 3.43 q2 display unit block diagram 56 (7) speech output: using the fpga, the NAV-DS4? speech output unit converts 32-bit stereo speech data (16 bits each for left and right channels) transferred from the sh7708 into serial speech data, which it outputs via a dac. the devices used are a ?d6376gs (manufactured by nec) for the dac and an epf8452atc100-3 for the fpga. figure 3.44 shows the speech output unit peripheral block diagram, and figure 3.45 shows an internal block diagram of the speech output fpga. the main components of the fpga are a clock generator, an interrupt controller, and a parallel-to- serial converter. the clock generator generates clocks lrck (selected by the status register) and clk (7.5 mhz) for output to the dac, using clk_sh (30 mhz). the interrupt controller issues interrupt requests to the sh7708 in synchronization with lrck. each time an interrupt is generated, the sh7708 transfers parallel data to the 32-bit buffer in the fpga. the transferred data is converted to serial data by the parallel-to-serial converter in synchronization with clk. then data synthesis is performed, and serial speech data is output to the dac. figure 3.46 and 3.47 show the functions of the speech output fpga registers. figure 3.48 shows the speech output unit timing chart. a0, a2:7 d0:31 _cs5 _rd _wr clk_sh _irl _reset lrck clk si a0:7 d0:31 _cs5 _rd _we0 ckio _irl0 _irl1 _irl2 _irl3 _reset cpu: sh7708 reset switch 30 mhz interrupt priority encoder _inrq11 speech output fpga: epf8452atc100-3 lrck clk si d.vdd a.vdd d.gnd a.gnd dac: m pd6376gs 5 v 5 v digital circuitry analog circuitry board side off-board speaker figure 3.44 speech output unit peripheral block diagram 57 interrupt request signal _inrq11 d0:31 speech data / fpga internal register read/ write data interrupt controller clock generator 32-bit buffer upper 16-bit parallel-to-serial converter data synthesis lower 16-bit parallel-to-serial converter serial data left/right identification signal 44.1/22.025 11.025/8.0 khz lrck 7.5 mhz clk serial data read clock si serial speech data figure 3.45 speech output fpga internal block diagram bit bit name initial value d31 dr31 0 d30 dr30 0 d29 . . . d2 . . . . . . d1 dr1 0 d0 dr0 0 the receive register is used to input speech data. it is a write-only register, and _irl is cleared after data is written. figure 3.46 receive register function 58 bit bit name initial value d31 . . . d4 not used 0 d3 11e 0 d2 22e 0 d1 44e 0 d0 dae 0 the status register is used for lrck signal selection (see table below). dae is used as adpcm_sw. lrck signal is not output. (adpcm_sw: off) lrck signal is output at 8 [khz]. lrck signal is output at 11.025 [khz]. lrck signal is output at 22.05 [khz]. lrck signal is output at 44.1 [khz]. set value 11e 0 0 1 function 22e 0 0 0 1 44e 0 0 0 0 1 dae 0 1 1 1 1 figure 3.47 status register settings and functions si adpcm_sw is generated by setting the dae flag in the status register. lrck, clk, and _irl are generated using clk_sh. clk_sh apsd_sw lrck _irl clk 30.0 mhz 7.5 mhz 44.1 khz, 22,05 khz, 11,05 khz, or 8.0 khz transmit data = 16 bits transmit data = 16 bits d31 d16 d15 d0 d31 figure 3.48 speech output unit timing chart 59 (8) scsi interface: the NAV-DS4 reads map data from a an external cd-rom drive containing a navigation cd-rom, and performs drawing and display based on this data. a scsi interface is used for the external cd-rom drive, and cpu transfer is used for data transfer. an sym53cf96- 2 (manufactured by symbiosis logic) is used for the scsi controller, and an epm7032lc44-6 (manufactured by altera) is mounted as the control fpga. since the scsi interface uses little- endian mode, the upper and lower bytes of the device are reversed for connection to the sh7708. figure 3.49 shows the scsi controller peripheral block diagram. a half-pitch 50-pin connector (female, shielded) is mounted, and single-end connection is used. 1514131211109876543210 7654321015141312111098 1514131211109876543210 pad0:7 db0:7 db8:15 a0:3 _rd _wr _cs _dbwr _dack dreq _int clk reset mode0 mode1 scsi: sym53cf96-2 d0:7 d0:7 d8:15 a1:4 a0, a2:7 30 mhz _inrq10 _inrq4 _cs dwe _dack dreq a0,a2:7 _cs1 _rd _we0 _we1 int scsi control fpga: epm7032lc44-6 reset switch data bus d0:15 address bus a0:25 _cs1 _rd _we0 _we1 _irl0 _irl1 _irl2 _irl3 ckio _reset cpu: sh7708 upper and lower data bytes reversed interrupt priority encoder cpu data d0:15 scsi data db0:15 off-board board side cd-rom drive scsi connector: nhs050-032-bs2 pull-up resistor 10 k w set to mode 3 dip switch 5 v figure 3.49 scsi controller peripheral block diagram 60 (9) key input interface: the NAV-DS4 is equipped with 16 switches mounted on the mother board, with an epf8282atc100-3 (manufactured by altera) used as the control fpga. momentary switching is used, in which the on-state is maintained while the switch is pressed. the fpga has an interrupt priority encoder function. figure 3.50 shows the key input fpga peripheral block diagram. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 switch layout on board pull-up resistors 10 k w 16 5 v 5 v sw0 sw15 dip switch 5 v _inrq1 _inrq15 . . . . . . . . . . . . . interrupt requests pull-up resistors 10 k w 8 pull-up resistors 10 k w 15 sw0:15 dsw0:7 ad0:5 d0:7 rd cs5 address bus a0:5 data bus d0:7 _rd _cs5 _irl3 _irl2 _irl1 _irl0 cpu: sh7708 key input fpga: epf8282atc100-3 interrupt priority encoder figure 3.50 key input fpga peripheral block diagram 61 (10) serial communication interface (sci): the NAV-DS4 can perform serial data exchange with a pc using the sh7708? on-chip sci. an max233acwp (manufactured by maxim) is used as the rs-232c driver. an rs-232c standard d-sub 9-pin (male) connector is used. a dip switch allows switching between cross and straight connection. figure 3.51 shows the sci peripheral block diagram. cpu: sh7708 t1out t2out r1in r2in vcc c2+ c2+ c2 c2 gnd gnd t1in t2in r1out r2out c1+ c1 v v v+ rs-232c driver: max233 acwp dip switch cross/ straight switching 5 v 10 m f + e dcd rxd txd dtr gnd dsr rts cts ri sci connector (rs-232c): 17ae-23090a-9750 (male) personal computer sci interface md1/txd md2/rxd sci off-board (female) board (male) side figure 3.51 sci peripheral block diagram 62 (11) expansion connectors: the NAV-DS4 is equipped with board-to-board expansion connectors that provide for functional expansion by means of hardware. the expansion connectors are intended for connection to 5 v systems, and a level shifter is used between the connected system and the sh7708. two hif7c-80pa-1.27dsal connectors (80-pin plug type, manufactured by hirose) are used, and hif7c-80da-1.27dsal units are required on the receptacle side. figure 3.52 shows the expansion connector peripheral block diagram. address bus a0:25 _irqout ckio _bs rd/_wr _rd _cs0 _cs1 _cs2 _cs5 _cs6 _we3 _we2 _cashh _cashl _we1 _we0 _caslh _casll _ras cke _reset _irqout ckio _bs rd/_wr _rd _cs0 _cs1 _cs2 _cs5 _cs6 _we3 _we2 _cashh _cashl _we1 _we0 _caslh _casll _ras cke _reset address bus a0:25 expansion connector a: hif7c-80pa-1.27dsal 5 v reset switch data bus d0:31 _iois16 _wait _inrq2 _inrq7 _inrq13 expansion connector b: hif7c-80pa-1.27dsal 5 v interrupt priority encoder cpu: sh7708 data bus d0:31 _iois16 _wait _irl0 _irl1 _irl2 _irl3 wait signal from q2 board (plug) side off-board (receptacle) figure 3.52 expansion connector peripheral block diagram 63 3.6 sh7708 and peripheral timing charts (1) sh7708 flash memory read timing t1 33.3ns tw1 33.3ns tw2 33.3ns t2 33.3ns t ad 15ns t csd1 14ns t rsd 14ns t rdh1 0ns (c) cpu data hold time t rdh1 0ns t rds1 12ns (d) flash memory data hold time t oh 0ns flash memory (a) time until cpu data read setup 104.55 ns t acc 80ns(max) t ce 80ns(max) t oe 40ns(max) decode circuit delay: 12 ns (b) time until flash memory outputs data 95 [ns] (worst case) ckio a25:0 _cs0 _rd d31:0 _ce _oe (_flaoe) i/o cpu 64 in case of 2-wait/4-cycle access to sh7708 flash memory: 1) data setup time: (a) time until cpu data read setup t1 + tw1 + tw2 + (t2/2) ?t rds1 = 33.3 + 33.3 + 33.3 + (33.3/2) ?12 = 104.55 [ns] (b) time until flash memory outputs data viewed from address: t ad + t acc = 15 + 80 = 95 [ns] ? worst case viewed from _ce: t csd1 + t ce = 14 + 80 = 94 [ns] viewed from _oe: (t1/2) + t rsd + decode circuit delay + t oe = (33.3/2) + 14 + 12 + 40 = 82.65 [ns] thus, (b) < (a), and the cpu setup time is satisfied. 2) data hold time: (c) cpu data hold time t rdh1 = 0 [ns] (d) flash memory data hold time t oh = 0 [ns] thus, (d) (c), and the cpu data hold time is satisfied. from 1) and 2), 2-wait/4-cycle access is possible. 65 (2) sh7708 sram read timing t1 33.3ns tw 33.3ns t2 33.3ns cpu t rdh1 0ns t rdh1 0ns t ad 15ns t csd1 14ns t rwd 14ns t rsd 14ns (a) time until cpu data read setup t rds1 12ns 71.25ns t oe 6ns (max) t lb , t ub 6ns(max) 42.65 [ns] (worst case) ckio a25:0 _cs2 rd/_wr _rd d31:0 _lb, _ub i/o sram t oh 3ns ttl circuit delayviewed from _rd: 6 ns (b) time until sram outputs data t aa 12ns (max) t acs 12ns (max) (c) cpu data hold time (d) sram data hold time 66 in case of 1-wait/3-cycle read access to sram: 1) data setup time: (a) time until cpu data read setup t1 + tw + (t2/2) ?t rds1 = 33.3 + 33.3 + (33.3/2) ?12 = 71.25 [ns] (b) time until sram outputs data viewed from address: t ad + t aa = 15 + 12 = 27 [ns] viewed from _cs2: t csd1 + t acs = 14 + 12 = 26 [ns] viewed from _rd: (t1/2) + t rsd + t oe = (33.3/2) + 14 + 6 = 36.65 [ns] viewed from _lb, _ub: (t1/2) + t rsd + ttl circuit delay + t lb , t ub = (33.3/2) + 14 + 6 + 6 = 42.65 [ns] ? worst case thus, (b) < (a), and the cpu setup time is satisfied. 2) data hold time: (c) cpu data hold time t rdh1 = 0 [ns] (d) sram data hold time (viewed from address) t oh = 3 [ns] thus, (d) (c), and the cpu data hold time is satisfied. from 1) and 2), 1-wait/3-cycle read access is possible. 67 (3) sh7708 sram write timing ckio a25:0 _cs2 rd/_wr _wen d31:0 _lb, _ub i/o t1 33.3ns tw 33.3ns t2 33.3ns cpu sram t ad 15ns t csd1 14ns t rwd 14ns t wed 14ns t lbw ,t ubw (min) 9ns t wdd1 17ns t oh 3ns t dw 6ns 39.65 [ns] (worst case) delay: 6 ns t wdh3 0ns (a) time until cpu data write setup ttl circuit delay viewed from _wen: 6 ns (c) cpu data hold time (b) time until sram inputs data (d) sram data hold time 68 in case of 1-wait/3-cycle write access to sram: 1) data setup time: (a) time until cpu data write setup t wdd1 = 17 [ns] (b) time until sram inputs data viewed from _lb, _ub: (t1/2) + t wed + ttl circuit delay + t lbw , t ubw ?t dw = (33.3/2) + 14 + 6 + 9 ?6 = 39.65 [ns] ? worst case thus, (b) > (a), and the cpu setup time is satisfied. 2) data hold time: (c) cpu data hold time (viewed from _wen) t wdh1 = 0 [ns] (d) sram data hold time t dh = 0 [ns] thus, (d) (c), and the cpu data hold time is satisfied. from 1) and 2), 1-wait/3-cycle write access is possible. 69 (4) sh7708 dram normal access read timing (edo mode) t ad _ras assert cycle tr 33.3ns trw 33.3ns tc 1 33.3ns tc 2 33.3ns (tpc) 33.3ns (tpc) 33.3ns row address t ad t ah t as 0ns t ad 15ns 0ns t as t ad t rwd 14ns t rwh 0ns 10ns t ah t rwd 15ns 15ns 15ns t rds2 t rdh2 cpu dram ckio a25?6 a15? rd/_wr _ras _casxx d31? _ras _ucas, _lcas a9:0 _we dout (a) time until cpu data read setup _cas assert cycle read data latch cycle _ras precharge interval in case of 2-wait/5-cycle access to dram, (b) (a), and the setup time is satisfied. (b) time until dram outputs data viewed from _ras: tr / 2 + t rasd1 + t rac = 91.65 ns viewed from _cas: tr + trw + tc1 / 2 + t casd1 + t cac = 113.25 ns ? worst case viewed from address: tr + trw + t ad + t aa = 111.6 ns t rc 104ns t ras 60ns t rp 40ns t crp 5ns t csh 48ns t rcd 20ns t cas 10ns t rad 15ns t rah 10ns r t asr 0ns c t cah 10ns t asc 0ns t rchr 60ns t rcs 0ns t ohr 3ns t cac 15ns t rac 60ns t rasd2 tr + trw + tc1 + tc2 e t rds2 = 121.2 ns 15ns t casd1 t casd1 15ns 15ns 15ns 14ns 10ns column address row address 6ns 12ns t ral 30ns t cal 30ns t aa 30ns t rch 0ns t rasd1 t rsh 15ns 70 (5) sh7708 dram normal access write timing (edo mode) t ad 15ns t ad 15ns row address t as 0ns t ad 15ns row address t rwd t ah 10ns column address t as 0ns t ad 15ns 10ns t ah t rwh 0ns t rwd 14ns 14ns t rasd2 15ns t rasd1 15ns t casd1 15ns t casd1 15ns t wdh3 0ns t wdh1 0ns t wds 0ns t wdd2 16ns (a) time until cpu data write setup t rp 40ns t rc 104ns t ras 60ns t crp 5ns t rsh 15ns t cas 10ns t rcd 20ns t csh 48ns t cah 10ns c t asc 0ns t rah 10ns t asr 0ns r t wch 10ns t wcs 0ns t ds 0ns t dh 10ns cpu dram tr 33.3ns trw 33.3ns tc 1 33.3ns tc 2 33.3ns (tpc) 33.3ns (tpc) 33.3ns _ras assert cycle _cas assert cycle _ras precharge interval ckio a25?6 a15? rd/_wr _ras _casxx d31? _ras _ucas, _lcas a9:0 _we dout tr + trw + t wdd2 = 33.3 + 33.3 + 16 = 82.6 ns tr + trw + tc1 / 2 + t casd1 ?t ds = 33.3 + 33.3 + (33.3/2) + 15 ?0 = 98.25 ns in case of 2-wait/5-cycle access to dram, (b) > (a), and the setup time is satisfied. (b) time until dram inputs data 71 (6) sh7708 dram burst access read timing (edo mode) t ad 15ns row address t as 0ns t ad 15ns t ad t as 15ns 0ns t ad 15ns t ah 10ns 15ns t ad column address column address row address t rwd 14ns 10ns t ah t ah 10ns t rwh 0ns t rwd 14ns 15ns t rasd2 15ns t casd1 t casd1 15ns 15ns t casd1 15ns t casd1 15ns t rasd1 t rdh2 6ns t rds2 12ns t rdh2 6ns t rds2 12ns t rp 40ns t rasp 10000ns(max) t crp 5ns t csh 48ns t cas 10ns t rsh 15ns t cp 10ns t cas 10ns t ral 30ns t cal 30ns t cah 10ns t asc 0ns t cal 30ns t cah 10ns t asc 0ns t rah 10ns t asr 0ns c c r t rch 0ns t rcs 0ns t ohr 3ns t cpa 35ns t cac 15ns t aa 30ns t cac 15ns t aa 30ns t rac 60ns ckio a25?6 a15? rd/_wr _casxx d31? _ras _ucas, _lcas a9:0 _we dout _ras tr 33.3ns trw 33.3ns tc 1 33.3ns tc 2 33.3ns tc 1 33.3ns tc 2 33.3ns (tpc) 33.3ns (tpc) 33.3ns _ras assert cycle _cas assert cycle read data latch cycle burst cycle = 2 cycles _cas assert cycle read data latch cycle _ras precharge interval cpu dram 72 (7) sh7708 dram burst access write timing (edo mode) t ad 15ns row address t as 0ns t ad 15ns t ad t as 15ns 0ns t ad 15ns t ah 10ns 15ns t ad column address column address row address t rwd 14ns 10ns t ah t ah 10ns t rwh 0ns t rwd 14ns 15ns t rasd2 15ns t casd1 t casd1 15ns 15ns t casd1 15ns t casd1 15ns t rasd1 t wdh3 0ns t rp 40ns t rasp 10000ns t csh 48ns t rcd 20ns t cas 5ns t rsh 15ns t cp 10ns t cas 10ns t cah 10ns t asc 0ns t cah 10ns t asc 0ns t rah 10ns t asr 0ns c c r t wch 10ns t wcs 0ns ckio a25?6 a15? rd/_wr _casxx d31? _ras _ucas, _lcas a9:0 _we dout _ras tr 33.3ns trw 33.3ns tc 1 33.3ns tc 2 33.3ns tc 1 33.3ns tc 2 33.3ns (tpc) 33.3ns (tpc) 33.3ns _ras assert cycle _cas assert cycle burst cycle = 2 cycles _cas assert cycle _ras precharge interval cpu dram t wdh1 0ns t wdd2 16ns t wdh3 0ns 0ns t wds t wdd2 16ns t crp 5ns t dh 10ns t ds 0ns t dh 10ns t ds 0ns 73 (8) sh7708 q2 read timing t1 33.3ns 33.3ns t2 33.3ns t3 33.3ns t4 33.3ns tw 33.3ns tw 33.3ns t5 33.3ns t1 33.3ns 33.3ns t ad 15ns t csd1 14ns 14ns t rsd decode circuit delay: 12 ns t ad 15ns 10ns t ah t csd2 14ns t rsd 14ns t rds1 12ns q2 cpu t rddh 4ns t wad 20ns t rddws 10ns t rddrs 66.6ns 20ns t wad cki0 a25:0 _cs4 _rd _cs1, 0 _rd _wait d15:0 d15:0 74 (9) sh7708 q2 write timing t1 33.3ns 33.3ns t2 33.3ns t3 33.3ns t4 33.3ns tw 33.3ns tw 33.3ns t5 33.3ns t1 33.3ns 33.3ns t ad 15ns t csd1 14ns 14ns t rsd decode circuit delay: 12 ns t ad 15ns 10ns t ah t csd2 14ns t wed 14ns q2 cpu t wrdh 0ns t wad 20ns t wrdws 0ns 20ns t wad cki0 a25:0 _cs4 _wen _cs1, 0 _wen _wait d15:0 d15:0 t wrdes 66.6ns 17ns t wdd1 sh graphics/speech processing demonstration system NAV-DS4 application note publication date: 1st edition, january 1998 published by: semiconductor and ic div. hitachi, ltd. edited by: technical documentation center hitachi microcomputer system ltd. co py ri g ht ?hitachi, ltd., 1998. all ri g hts reserved. printed in ja p an. |
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